This invention relates to semiconductor memory devices, and more particularly to data input/output circuits for dynamic memory devices having serial I/O modes.
Dynamic MOS read/write memory devices have been constructed generally as shown in U.S. Pat. No. 4,081,701 (a 16K dynamic RAM) issued to White, McAdams and Redwine, or U.S. Pat. No. 4,293,993 (a 64K dynamic RAM) issued to McAlexander, White and Rao, both assigned to Texas Instruments. In these prior devices the data input/output was of the single-bit format. In U.S. Pat. No. 4,330,852 issued to Redwine, White and Rao, also assigned to Texas Instruments, a dynamic RAM is shown which provides both random access and serial access capability for data I/O.
The manufacture of memory devices is much more economical if a single chip design is produced in high volume rather than smaller numbers of several different designs. However, several different types of data I/O capabilities for DRAMs are required by various customers. Examples of these are nibble mode (4-bit serial), byte mode (8-bit serial), extended nibble, etc. Each of these would require different I/O circuitry, and thus a different chip design.
It is the principal object of this invention to provide improved data input/output circuitry for high density dynamic RAM devices, particularly for serial data I/O modes. Another object is to provide data input/output circuitry for a CMOS dynamic RAM in which the operating mode may be changed by relatively simple changes at a late stage in the manufacturing process. A further object is to provide serial data I/O circuitry which is of high speed and low power dissipation.